1. Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to the stabilization of a reference potential for use in detecting a data read out from a memory cell.
2. Description of the Related Art
A conventional EPROM (erasable and programmable read only memory) is shown in FIG. 1. MC11, MC12 ..., MC1n, ..., MCmn designate memory cells comprised of floating gate MOSFETs (metal oxide semiconductor field effect transistors). DC1, DC2, ..., DCm designate dummy memory cells comprised of floating gate MOSFETs. WL1, WL2, ... WLm are row lines. BL1, BL2, ..., BLn are normal column lines. DBL designates a dummy column line.
Reference numerals 11 and 12 denote a row decoder and a column decoder, respectively. BT1, BT2, ..., BTn denote column gate MOSFETs for selecting one of column lines BL1, BL2, ..., BLn, respectively. DBT designates a MOSFET corresponding to the column gate MOSFET for dummy column line DBL. MOSFET DBT is substantially identical to column gate MOSFET BT (a general designation of BT1, BT2, ..., BTn). The gate of MOSFET DBT is supplied with a power source voltage so that MOSFET DBT is normally turned conductive. First load circuit 13 comprises MOSFETs QM1 to QM12 and generates a potential Vin. Second load circuit 14 comprises MOSFETS QD1 to QD12 and generates a reference potential Vref. Data detecting circuit 15 comprises a sense amplifier.
In the EPROM as shown in FIG. 1, data detecting circuit 15 compares reference potential Vref with potential Vin. Reference potential Vref is generated by second load circuit 14, based on the data read out from a selected dummy memory cell DC (a general designation of DC1, DC2, ..., DCm). Potential Vin is generated by first load circuit 13, based on the data read out from a selected normal memory cell MC (a general designation of MC11, MC12, ..., MC1n, ..., MCmn). Through the comparison, the data stored in the selected, normal memory cell MC is detected.
The MOSFET of a dummy memory cell DC is substantially identical to the MOSFET of a normal memory cell MC. Dummy column line DBL is substantially identical to a normal column line BL (a general designation of BL1, BL2, ..., BLn).
The current supply ability of the load MOSFET QD5 in second load circuit 14 is larger than that of load MOSFET QM5 in first load circuit 13 to provide a potential difference between the potentials Vref and Vin, so that data can be detected. If the current supply abilities of the first and second load circuits are the same, data can not be detected. Specifically, in the memory cells of such an EPROM, electrons are injected into the floating gate of a memory cell to write data "0" thereinto. On the other hand, electrons are not injected in the floating gate of a memory cell to write data "1" thereinto. A memory cell in which electrons are injected is kept off, even when a logic "1" signal is applied to the control gate. On the other hand, a memory cell in which electrons are not injected is turned on, when a logic "1" signal is applied to the control gate. No electrons are injected into the dummy memory cell. Therefore, the logic state of the dummy memory cell is substantially the same as that of a normal memory cell in which electrons are not injected. If the current supply ability of the MOSFET QD5 is equal to that of the MOSFET QM5, no difference occurs between potentials Vref and Vin. In this case, data can not be detected. In order to detect data, it is necessary to provide a difference between potentials Vref and Vin. This is the reason why the current supply ability of the MOSFET QD5 is larger than that of the MOSFET QM5. The current supply ability difference causes a potential difference between potential Vref and Vin, even when a normal memory cell in which electrons are not injected is selected.
The current supply ability difference can be obtained by using the different channel widths of the load MOSFETs in first and second load circuits 13 and 14. Assume, for example, the channel width of MOSFET QM5 is denoted by W5, its channel length by L, the channel width of MOSFET QD5 by W6, and its channel length by L. In this case W6&gt;W5. so that a current supply ability difference can be obtained between the load MOSFETs QD5 and QM5.
When the MOSFET QM1, QM2, QM3, and QM4 in first load circuit 13 are sized to be W1/L, W2/L, W3/L and W4/L, respectively, then the MOSFET QD1, QD2, QD3, and QD4 in second load circuit 14 are also designed to have the size of W1/L, W2/L, W3/L and W4/L, respectively. Further, W1&gt;W2 and W3&gt;W4. And, MOSFETs QM8, QM9, QD8, and QD9 have the same size.
In the above memory device arrangement, to generate reference potential Vref, dummy memory cell DC is connected to row line WL (a general designation of WL1, WL2, ... WLn), dummy column line DBL is connected to dummy memory cell DC, and dummy column line DBL is connected to second load circuit 14. This circuit arrangement can provide reference potential Vref stable against the power source noise. The reason for this is that dummy column line DBL is substantially identical to normal column line BL and, thus, the stray capacitances of the dummy column line and the normal column line are substantially equal to each other. Because of the capacitances being equal, the potential variation on column line BL and dummy column line DBL are substantially equal, even when the power source potential varies. Consequently, data detecting circuit 15 can perform a correct data detection.
In such EPROM, since, however, dummy cells DC are connected to row lines WL, reference potential Vref varies during the transient period of a switching of the row lines.
FIG. 2 shows waveforms of signals at varies portions in the conventional memory device shown in FIG. 1. When a logic state of row line WL2 changes from "1" to "0", and, at the same time, a logic state of row line WL1 changes from "0" to "1", potential Vin becomes a logic "1", and data detecting circuit 15 outputs a logic "1". During the transient period of this row line switching, no row lines are selected. In this transient period, the row line WL2 to be discharged to a logic "0" and the row line WL1 to be charged to a logic "1" are both at medium potential between a logic "1" and a logic "0". In the nonvolatile semiconductor memory cells of floating gate MOSFETs, the threshold voltage of the memory cell is generally high, e.g., 2 V. So, the sum of the currents flowing through dummy memory cell DC2 and dummy memory cell DC1 when the row lines WL1 and WL2 are at the medium potential is smaller than that of the current flowing through one dummy memory cell when the row line is perfectly in a logic "1". As a result, as shown in FIG. 2, reference potential Vref rises when in the transient period of the row line switching.
When the potential difference between potentials Vref and Vin is larger, the data detection is easier, and the data detection time of data detecting circuit 15 is shortened. When, on the other hand, the potential difference is smaller, the data detection is more sensitive to noise so that data detecting circuit 15 may perform an erroneous operation.
In the conventional memory device of the type using a dummy column line, during the transient period of the row lines (during the logic level of potential Vin changes), potential Vref varies and approaches to potential Vin, so that the difference between these potential Vref and Vin becomes smaller. If, therefore, noise occurs during this transient period, data detecting circuit 15 will possibly perform an erroneous data detection.